Author(s)
Thomas Pickell, Bert Hochwald, Randy Herban, and Christopher Wahl
Abstract
The RadioHound project requires a significant increase in its data sampling rate, which is currently limited to 48MHz. This research focuses on the design and implementation of a high-speed data acquisition system built to overcome this limitation. The primary objective is to stream data from RadioHound’s analog-to-digital converter (ADC) through the Field-Programmable Gate Array (FPGA) fabric of a BeagleV-Fire board and into its main DDR memory at the highest possible throughput. The system architecture creates a direct data path from the ADC to memory, which minimizes CPU overhead. It utilizes Microchip’s CoreAXI4DMAController IP, an intellectual property core capable of achieving transfer rates up to 7488 Mb/s. This controller is paired with a custom Verilog module that aggregates eight 8-bit samples into a single 64-bit word to maximize the efficiency of the 64-bit AXI4 bus. Control is managed by bare-metal C drivers that configure the Processor peripherals for DMA access and set up DMA operations using descriptors in a non-cached memory region, a critical choice to prevent CPU cache coherency problems. The foundational C drivers for memory and DMA control have been successfully developed and verified. A key validation test, which performs a DMA transfer between two separate locations within DDR memory, passes successfully. This result confirms that the MPU is configured correctly and that the DMA controller can read from and write to memory as designed. This work establishes the essential infrastructure needed to greatly increase RadioHound’s sampling rate and provide a full concept for integration into a RadioHound Node.